`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:30:15 03/05/2013
// Design Name:   sig_hys
// Module Name:   C:/Users/Vincent/Documents/Spring 2013/CSE 320/Project 1/sig_hys/tb/tb_sig_hys_case1.v
// Project Name:  sig_hys
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: sig_hys
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_sig_hys_case1;

	// Inputs
	reg dir_sig;
	reg clk;
	reg reset_b;

	// Outputs
	wire fil_sig;

	// Instantiate the Unit Under Test (UUT)
	sig_hys uut (
		.dir_sig(dir_sig), 
		.clk(clk), 
		.reset_b(reset_b), 
		.fil_sig(fil_sig)
	);

	initial begin
	forever #5 clk <= ~clk;
	end
	
	initial begin
		// Initialize Inputs
		dir_sig = 0;
		clk = 0;
		reset_b = 0;

		// Wait 100 ns for global reset to finish
		
        
		// Add stimulus here

	#21 reset_b = 1'b1; dir_sig = 1'b0;
	#1 reset_b = 1'b1; dir_sig = 1'b1;
	#11 reset_b = 1'b1; dir_sig = 1'b0; 
	#5 reset_b = 1'b1; dir_sig = 1'b1;
	#18 reset_b = 1'b1; dir_sig = 1'b0;	//56
	#29 reset_b = 1'b1; dir_sig = 1'b1;
	#70 reset_b = 1'b1; dir_sig = 1'b0; //155
	
	end
      
endmodule

